Fixed-Width Multiplier Circuits Using Column Bypassing and Decompositon Logic Techniques

This paper presents, low power signed and unsigned fixed-width multipliers using the column bypassing technique with carry save adder array structure. We have decomposed the partial products into two parts and executed them in parallel to reduce the delay of proposed fixed-width array multiplier. The proposed multiplier reduces the power consumption by skipping the unwanted switching activity when the multiplicand operand consists of a number of zeros. This work evaluates the power, delay and area of fixed-width multipliers and shows that the proposed array multiplier consumes less power and has reduced delay compared to the conventional fixed-width array multipliers.